Managing power loss recovery using a dirty section write policy for an address mapping table in a memory sub-system
US11940912B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 1, 2022 |
| Grant date | Mar 26, 2024 |
| Priority date | — |
| Expiry date | Jun 11, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7208
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A logical-to-physical (L2P) table is maintained, wherein a plurality of sections of the L2P table is cached in a volatile memory device. A total dirty count for the L2P table is maintained, wherein the total dirty count reflects a total number of updates to the L2P table. Respective section dirty counts for the plurality of sections are maintained, wherein each respective section dirty count reflects a total number of updates to a corresponding section. It is determined that the total dirty count for the L2P table satisfies a threshold criterion. In response to determining that the total dirty count for the L2P table satisfies the threshold criterion, a first section of the plurality of sections is identified based on the respective section dirty counts. The first section of the L2P table is written to a non-volatile memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.