Automated equal-resistance routing in compact pattern
US11941339B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 2022 |
| Grant date | Mar 26, 2024 |
| Priority date | — |
| Expiry date | Sep 24, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described is technology for automatically generating a routing for an integrated circuit (IC) design. Information describing pin-pairs of an integrated circuit (IC) design is received. An initial routing of the IC design is determined by (i) defining connected wires between each pin-pair in the set of pin-pairs, and (ii) evaluating a target resistance for the pin-pair over the connected wires, wherein each connected wire is routed with other connected wires. A resistance adjustment is applied to adjust wire resistance of the connected wires of the initial routing. The resistance adjustment can be based on a square routing in response to a wire resistance being below the target resistance; or the resistance adjustment can be based on a multi-layer stacking in response to the wire resistance being above the target resistance. The routing is provided in patterns as generated by the initial routing and the resistance adjustment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.