Through silicon vias and methods of fabricating thereof
US11942368B2 · kind B2 · utility
1Cited by
5References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 2, 2021 |
| Grant date | Mar 26, 2024 |
| Priority date | — |
| Expiry date | Dec 20, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/522
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods and devices of having an enclosure structure formed in a multi-layer interconnect and a through-silicon-via (TSV) extending through the enclosure structure. In some implementations, a protection layer is formed between the enclosure structure and the TSV.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.