Fin isolation structure for FinFET and method of forming the same
US11942373B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 10, 2023 |
| Grant date | Mar 26, 2024 |
| Priority date | — |
| Expiry date | May 10, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31053
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device structure is provided. The semiconductor device structure includes a first fin, a second fin and a third fin therebetween. A first insulating structure includes a first insulating layer formed between the first and third fins, a capping structure covering the first insulating layer, a first insulating liner covering sidewall surfaces of the first insulating layer and the capping structure and a bottom surface of the first insulating layer, and a second insulating liner formed between the first insulating liner and the first fin and between the first insulating liner and the third fin. The second insulating structure includes a second insulating layer formed between the second fin and the third fin and a third insulating liner formed between the second insulating layer and the second fin and between the second insulating layer and the third fin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.