Symmetric layout for high-voltage amplifier
US11942468B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 25, 2021 |
| Grant date | Mar 26, 2024 |
| Priority date | — |
| Expiry date | Sep 16, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/03
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A packaged semiconductor die may include a package terminal array comprising a plurality of terminals, wherein a spacing between the plurality of terminals of the ball grid array is less than 0.5 mm. First and second high-voltage circuits of the die may output a differential signal to a first and second terminal that may exceed 15 volts, in which the first high-voltage circuit and the second high-voltage circuit are positioned symmetrically around an axis and in which the first terminal and the second terminal are located at an edge of the package terminal array. A low-voltage circuit may be coupled to a third terminal and positioned between the first high-voltage circuit and the second high-voltage circuit, wherein the low-voltage circuit comprises circuitry organized in columns aligned along an axis and having a width defined by a fraction of the terminal spacing pitch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.