Systems and methods for digital predistortion to mitigate power amplifier bias circuit effects
US11942904B2 · kind B2 · utility
0Cited by
8References
20Claims
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Key dates
| Filing date | Aug 16, 2021 |
| Grant date | Mar 26, 2024 |
| Priority date | — |
| Expiry date | Jan 28, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2201/3227
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital predistortion (DPD) system includes an input configured to receive an input signal. In some examples, a first signal path configured to generate a first signal based on the input signal. In some examples, an error model provider configured to generate an error model signal modeled after a gate bias error voltage associated with the DPD system. In some examples, a first combiner configured to combine the first signal and the error model signal to generate a first intermediate signal, and the DPD system generates an output signal based at least on the first intermediate signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.