Non-volatile memory device with vertical state transistor and vertical selection transistor
US11943931B2 · kind B2 · utility
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3References
17Claims
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Key dates
| Filing date | Apr 1, 2021 |
| Grant date | Mar 26, 2024 |
| Priority date | — |
| Expiry date | May 28, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6894
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a non-volatile memory device includes a vertical state transistor disposed in a semiconductor substrate, where the vertical state transistor is configured to trap charges in a dielectric interface between a semiconductor well and a control gate. A vertical selection transistor is disposed in the semiconductor substrate. The vertical selection transistor is disposed under the state transistor, and configured to select the state transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.