Gang scheduling for low-latency task synchronization
US11948000B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2021 |
| Grant date | Apr 2, 2024 |
| Priority date | — |
| Expiry date | Jun 16, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, apparatuses, and methods for performing command buffer gang submission are disclosed. A system includes at least first and second processors and a memory. The first processor (e.g., CPU) generates a command buffer and stores the command buffer in the memory. A mechanism is implemented where a granularity of work provided to the second processor (e.g., GPU) is increased which, in turn, increases the opportunities for parallel work. In gang submission mode, the user-mode driver (UMD) specifies a set of multiple queues and command buffers to execute on those multiple queues, and that work is guaranteed to execute as a single unit from the GPU operating system scheduler point of view. Using gang submission, synchronization between command buffers executing on multiple queues in the same submit is safe. This opens up optimization opportunities for application use (explicit gang submission) and for internal driver use (implicit gang submission).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.