Accelerated embedding layer computations
US11948086B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 2023 |
| Grant date | Apr 2, 2024 |
| Priority date | — |
| Expiry date | Apr 21, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/084
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and apparatus, including computer-readable media, are described for performing neural network computations using a system configured to implement a neural network on a hardware circuit. The system includes a host that receives a batch of inputs to a neural network layer. Each of the inputs is stored in a memory location identified by an address. The system identifies one or more duplicate addresses in a listing of addresses for one or more inputs. For each duplicate address: the system generates a unique identifier that identifies the duplicate address in the listing of addresses. The system (i) obtains first inputs from memory locations identified by addresses corresponding to the unique identifiers and (ii) generates an output of the layer from the obtained first inputs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.