Wafer placement table
US11948825B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 3, 2021 |
| Grant date | Apr 2, 2024 |
| Priority date | — |
| Expiry date | Jul 26, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02N13/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wafer placement table includes: an electrostatic chuck that is a ceramic sintered body in which an electrode for electrostatic adsorption is embedded; a cooling member which is bonded to a surface on an opposite side of a wafer placement surface of the electrostatic chuck, and cools the electrostatic chuck; a hole for power supply terminal, the hole penetrating the cooling member in a thickness direction; and a power supply terminal which is bonded to the electrode for electrostatic adsorption from the surface on the opposite side of the wafer placement surface of the electrostatic chuck, and is inserted in the hole for power supply terminal. The outer peripheral surface of a portion of the power supply terminal is covered with an insulating thin film that is formed by coating of an insulating material, the portion being inserted in the hole for power supply terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.