Etch barrier for microelectronic packaging conductive structures
US11948898B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 16, 2019 |
| Grant date | Apr 2, 2024 |
| Priority date | — |
| Expiry date | Jun 19, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/124
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Conductive structures in a microelectronic package and having a surface roughness of 50 nm or less are described. This surface roughness is from 2 to 4 times less than can be found in packages with conductive structures (e.g., traces) formed using alternative techniques. This reduced surface roughness has a number of benefits, which in some cases includes a reduction of insertion loss and improves a signal to noise ratio for high frequency computing applications. The reduced surface roughness can be accomplished by protecting the conductive structure r during etch processes and applying an adhesion promoting layer to the conductive structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.