Methods of forming stacked semiconductors die assemblies
US11948921B2 · kind B2 · utility
0Cited by
3References
16Claims
0Family size
Inventors
Key dates
| Filing date | Sep 15, 2022 |
| Grant date | Apr 2, 2024 |
| Priority date | — |
| Expiry date | Sep 15, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate and the components are connected with conductive material in preformed holes in dielectric material in the bond lines aligned with TSVs of the devices and the exposed conductors of the substrate. Methods of fabrication are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.