Owen R. Fay
108Patents
10h-index
59Co-inventors
83Inventor score
Filing activity: Apr 19, 1999 → May 20, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7015075B2 | Die encapsulation using a porous carrier | Electricity | 173 | Expired |
| US6953985B2 | Wafer level MEMS packaging | Electricity | 76 | Expired |
| US7425464B2 | Semiconductor device packaging | Electricity | 73 | Active |
| US7595226B2 | Method of packaging an integrated circuit die | Electricity | 59 | Active |
| US6930032B2 | Under bump metallurgy structural design for high reliability bumped packages | Electricity | 26 | Expired |
| US7078796B2 | Corrosion-resistant copper bond pad and integrated device | Electricity | 24 | Expired |
| US6362089B1 | Method for processing a semiconductor substrate having a copper surface disposed thereon and structure formed | Emerging Cross-Sectional Technologies | 23 | Expired |
| US7872332B2 | Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods | Electricity | 14 | Active |
| US6780751B2 | Method for eliminating voiding in plated solder | Electricity | 12 | Expired |
| US9418926B1 | Package-on-package semiconductor assemblies and methods of manufacturing the same | Electricity | 11 | Active |
| US11386004B2 | Memory device interface and method | Electricity | 8 | Active |
| US8435836B2 | Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods | Electricity | 7 | Active |
| US8659153B2 | Pillar on pad interconnect structures, semiconductor dice and die assemblies including such interconnect structures, and related methods | Electricity | 6 | Active |
| US10529592B2 | Semiconductor device assembly with pillar array | Electricity | 6 | Active |
| US9595513B2 | Proximity coupling of interconnect packaging systems and methods | Electricity | 6 | Active |
| US10297561B1 | Interconnect structures for preventing solder bridging, and associated systems and methods | Electricity | 5 | Active |
| US10032703B2 | Package-on-package semiconductor assemblies and methods of manufacturing the same | Electricity | 4 | Active |
| US9165888B2 | Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods | Electricity | 4 | Active |
| US9601374B2 | Semiconductor die assembly | Electricity | 3 | Active |
| US11081460B2 | Methods and systems for manufacturing pillar structures on semiconductor devices | Electricity | 3 | Active |
| US10872835B1 | Semiconductor assemblies including vertically integrated circuits and methods of manufacturing the same | Electricity | 3 | Active |
| US10381297B2 | Package-on-package semiconductor assemblies and methods of manufacturing the same | Electricity | 3 | Active |
| US10600750B2 | Interconnect structures for preventing solder bridging, and associated systems and methods | Electricity | 3 | Active |
| US11362070B2 | Microelectronic device assemblies and packages including multiple device stacks and related methods | Electricity | 3 | Active |
| US11456284B2 | Microelectronic device assemblies and packages and related methods | Electricity | 3 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.