Isolation structures in multi-gate semiconductor devices and methods of fabricating the same
US11948998B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 2022 |
| Grant date | Apr 2, 2024 |
| Priority date | — |
| Expiry date | Jul 28, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes forming a semiconductor substrate having an oxide layer embedded therein, forming a multi-layer (ML) stack including alternating channel layers and non-channel layers over the semiconductor substrate, forming a dummy gate stack over the ML, forming an S/D recess in the ML to expose the oxide layer, forming an epitaxial S/D feature in the S/D recess, removing the non-channel layers from the ML to form openings between the channel layers, where the openings are formed adjacent to the epitaxial S/D feature, and forming a high-k metal gate stack (HKMG) in the openings between the channel layers and in place of the dummy gate stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.