Dynamic allocation of computing resources for electronic design automation operations
US11954419B2 · kind B2 · utility
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12References
12Claims
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Key dates
| Filing date | Oct 22, 2018 |
| Grant date | Apr 9, 2024 |
| Priority date | — |
| Expiry date | Feb 4, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/373
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system may include a set of compute engines. The compute engines may be configured to perform electronic design automation (EDA) operations on a hierarchical dataset representative of an integrated circuit (IC) design. The system may also include a dynamic resource balancing engine configured to allocate computing resources to the set of compute engines and reallocate a particular computing resource allocated to a first compute engine based on an operation priority of an EDA operation performed by a second compute engine, an idle indicator for the first compute engine, or a combination of both.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.