Reduced memory write requirements in a system on a chip using automatic store predication
US11954496B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2021 |
| Grant date | Apr 9, 2024 |
| Priority date | — |
| Expiry date | Aug 11, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8061
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In various examples, systems and methods for reducing written requirements in a system on chip (SoC) are described herein. For instance, a total number of iterations may be determined for processing data, such as data representing an array. In some circumstances, a set of iterations may include a first number of iterations that is less than a second number of iterations. As such, and during execution of the set of iterations, a predicate flag corresponding to an excess iteration of the set of iterations may be generated, where the excess iteration corresponds to an iteration that is part of a number of excess iterations that is associated with a difference between the first number of iterations and the second number of iterations. Based on the predicate flag, one or more first values corresponding to the iteration may be prevented from being written to memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.