Variable width bounding volume hierarchy nodes
US11954788B2 · kind B2 · utility
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1References
18Claims
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Key dates
| Filing date | Dec 28, 2021 |
| Grant date | Apr 9, 2024 |
| Priority date | — |
| Expiry date | Dec 28, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2210/21
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique for performing ray tracing operations is provided. The technique includes processing small bounding box nodes in a box intersection test circuit to generate intersection test results for the small bounding box nodes; and processing large bounding box nodes in the box intersection test circuit to generate intersection test results for the large bounding box nodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.