Asynchronous signal to command timing calibration for testing accuracy
US11955160B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Jun 22, 2022 |
| Grant date | Apr 9, 2024 |
| Priority date | — |
| Expiry date | Nov 10, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A delay circuit is coupled to a memory device. At least a portion of the delay circuit is disposed in one or more memory banks on one or more memory chips of the memory device. The delay circuit is configured to calibrate an asynchronous signal received at each of the one or more memory banks so that the calibrated asynchronous signal has a common timing relationship with a respective internal command signal received at the corresponding memory bank for all of the one or more memory banks on the memory device. The calibrated asynchronous signals are used in various internal test operations to improve testing accuracy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.