Patent · US Active

Package stacking using chip to wafer bonding

US11955462B2 · kind B2 · utility

1Cited by

0References

20Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Georg Seidemann · Landshut, DE
Klaus Reingruber · Langquaid, DE
Christian Geissler · Teugn, DE
Sven Albers · Regensburg, DE
Andreas Wolter · Regensburg, DE
Marc Dittes · Regensburg, DE
Richard Patten · Minneapolis, US

Key dates

Filing date	Dec 16, 2021
Grant date	Apr 9, 2024
Priority date	—
Expiry date	Jun 30, 2042

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/3511
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.