Inventor · Landshut, DE

Georg Seidemann

81Patents
4h-index
65Co-inventors
65Inventor score

Filing activity: Jul 31, 2007 → Dec 27, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US9997444B2 Microelectronic package having a passive microelectronic device disposed within a package body Electricity 37 Active
US10319688B2 Antenna on ceramics for a packaged die Electricity 17 Active
US8779564B1 Semiconductor device with capacitive coupling structure Electricity 9 Active
US10403609B2 System-in-package devices and methods for forming system-in-package devices Electricity 6 Active
US10186499B2 Integrated circuit package assemblies including a chip recess Electricity 4 Active
US9142475B2 Magnetic contacts Electricity 4 Active
US10115668B2 Semiconductor package having a variable redistribution layer thickness Electricity 3 Active
US7660175B2 Integrated circuit, method for acquiring data and measurement system Physics 3 Active
US9368461B2 Contact pads for integrated circuit packages Electricity 3 Active
US9209143B2 Die edge side connection Electricity 3 Active
US11031699B2 Antenna with graded dielectirc and method of making the same Electricity 2 Active
US11270941B2 Bare-die smart bridge connected with copper pillars for system-in-package apparatus Electricity 2 Active
US10553538B2 Semiconductor package having a variable redistribution layer thickness Electricity 2 Active
US10209466B2 Integrated circuit packages including an optical redistribution layer Physics 2 Active
US11955462B2 Package stacking using chip to wafer bonding Electricity 1 Active
US11735570B2 Fan out packaging pop mechanical attach method Electricity 1 Active
US10522485B2 Electrical device and a method for forming an electrical device Electricity 1 Active
US9819327B2 Bulk acoustic wave resonator tuner circuits Electricity 1 Active
US11134573B2 Printed wiring-board islands for connecting chip packages and methods of assembling same Emerging Cross-Sectional Technologies 1 Active
US9397019B2 Integrated circuit package configurations to reduce stiffness Electricity 1 Active
US10672731B2 Wafer level package structure with internal conductive layer Electricity 1 Active
US10366968B2 Interconnect structure for a microelectronic device Electricity 1 Active
US10714455B2 Integrated circuit package assemblies including a chip recess Electricity 1 Active
US10263106B2 Power mesh-on-die trace bumping Electricity 1 Active
US12080655B2 Method to implement wafer-level chip-scale packages with grounded conformal shield Electricity 1 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.