Semiconductor device and method of forming vertical interconnect structure for PoP module
US11955467B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2021 |
| Grant date | Apr 9, 2024 |
| Priority date | — |
| Expiry date | Jan 22, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/1058
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device has a substrate and a first light sensitive material formed over the substrate. A plurality of first conductive posts is formed over the substrate by patterning the first light sensitive material and filling the pattern with a conductive material. A plurality of electrical contacts is formed over the substrate and the conductive posts are formed over the electrical contacts. A first electric component is disposed over the substrate between the first conductive posts. A plurality of second conductive posts is formed over the first electrical component by patterning a second light sensitive material and filling the pattern with conductive material. A first encapsulant is deposited over the first electrical component and conductive posts. A portion of the first encapsulant is removed to expose the first conductive posts. A second electrical component is disposed over the first electrical component and covered with a second encapsulant.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.