STATS ChipPAC Pte. Ltd.
392Patents
392Active
392Granted
62Portfolio score
Filing activity: Dec 3, 2007 → Apr 15, 2024 · 2 expiring within 5 years
Most-cited patents
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9385006B2 | Semiconductor device and method of forming an embedded SOP fan-out package | Electricity | 62 | Active |
| US9443797B2 | Semiconductor device having wire studs as vertical interconnect in FO-WLP | Electricity | 53 | Active |
| US9679863B2 | Semiconductor device and method of forming interconnect substrate for FO-WLCSP | Electricity | 52 | Active |
| US9735113B2 | Semiconductor device and method of forming ultra thin multi-die face-to-face WLCSP | Electricity | 48 | Active |
| US9385009B2 | Semiconductor device and method of forming stacked vias within interconnect structure for Fo-WLCSP | Electricity | 46 | Active |
| US9508626B2 | Semiconductor device and method of forming openings in thermally-conductive frame of FO-WLCSP to dissipate heat and reduce package height | Electricity | 46 | Active |
| US9397050B2 | Semiconductor device and method of forming pre-molded semiconductor die having bumps embedded in encapsulant | Electricity | 45 | Active |
| US9524955B2 | Semiconductor device and method of forming no-flow underfill material around vertical interconnect structure | Electricity | 44 | Active |
| US9406619B2 | Semiconductor device including pre-fabricated shielding frame disposed over semiconductor die | Electricity | 42 | Active |
| US9496152B2 | Carrier system with multi-tier conductive posts and method of manufacture thereof | Emerging Cross-Sectional Technologies | 41 | Active |
| US9893045B2 | Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect | Electricity | 30 | Active |
| US9842798B2 | Semiconductor device and method of forming a PoP device with embedded vertical interconnect units | Electricity | 28 | Active |
| US9837484B2 | Semiconductor device and method of forming substrate including embedded component with symmetrical structure | Electricity | 27 | Active |
| US9786623B2 | Semiconductor device and method of forming PoP semiconductor device with RDL over top package | Electricity | 22 | Active |
| US9527723B2 | Semiconductor device and method of forming microelectromechanical systems (MEMS) package | Electricity | 20 | Active |
| US9391046B2 | Semiconductor device and method of forming 3D semiconductor package with semiconductor die stacked over semiconductor wafer | Electricity | 18 | Active |
| US9941207B2 | Semiconductor device and method of fabricating 3D package with short cycle time and high yield | Electricity | 17 | Active |
| US10049964B2 | Semiconductor device and method of forming a fan-out PoP device with PWB vertical interconnect units | Electricity | 16 | Active |
| US9368563B2 | Semiconductor device including integrated passive device formed over semiconductor die with conductive bridge and fan-out redistribution layer | Electricity | 15 | Active |
| US9806040B2 | Antenna in embedded wafer-level ball-grid array package | Electricity | 14 | Active |
| US10453785B2 | Semiconductor device and method of forming double-sided fan-out wafer level package | Electricity | 13 | Active |
| US9685350B2 | Semiconductor device and method of forming embedded conductive layer for power/ground planes in Fo-eWLB | Electricity | 13 | Active |
| US9548240B2 | Semiconductor device and method of forming repassivation layer for robust low cost fan-out semiconductor package | Electricity | 12 | Active |
| US9875911B2 | Semiconductor device and method of forming interposer with opening to contain semiconductor die | Electricity | 12 | Active |
| US9837303B2 | Semiconductor method and device of forming a fan-out device with PWB vertical interconnect units | Electricity | 12 | Active |
Source: USPTO / EPO open patent data. Counts and citation impact are objective bibliographic measures.