RF MOS varactor
US11955530B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 2021 |
| Grant date | Apr 9, 2024 |
| Priority date | — |
| Expiry date | Oct 29, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/116
Abstract
An integrated circuit includes a substrate having a first conductivity type. A well formed at an upper surface has a second, opposite conductivity type and a first dopant concentration. First and second STI structures are formed and a polysilicon gate structure is formed between the first and second STI structures. The polysilicon gate structure extends over a first side of the first STI structure and over a first side of the second STI structure. A first doped region is formed within the well at the upper surface and on a second side of the first STI structure and a second doped region is formed within the well at the upper surface and on a second side of the second STI structure. The first and second doped regions each have the second conductivity type and a second dopant concentration that is greater than the first dopant concentration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.