Reliable link management for a high-speed signaling interconnect
US11956342B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2022 |
| Grant date | Apr 9, 2024 |
| Priority date | — |
| Expiry date | Nov 16, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/14
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system includes a link having one or more lanes associated with transmitting data and one or more lanes associated with transmitting a clock signal. The system includes a device coupled with the link, the device to receive a signal via the one or more lanes associated with transmitting the clock signal and determine a number of pulses associated with the signal over a period. The device is further to determine the number of pulses associated with the signal fail to satisfy a predetermined condition relating to a specified number of pulses for the period and initiate a power-down sequence in response to determining the number of pulses that fail to satisfy the predetermined condition relating to the specified number of pulses for the period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.