System and method for large memory transaction (LMT) stores
US11960727B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2022 |
| Grant date | Apr 16, 2024 |
| Priority date | — |
| Expiry date | Oct 29, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and corresponding method perform large memory transaction (LMT) stores. The system comprises a processor associated with a data-processing width and a processor accelerator. The processor accelerator performs a LMT store of a data set to a coprocessor in response to an instruction from the processor targeting the coprocessor. The data set corresponds to the instruction. The LMT store includes storing data from the data set, atomically, to the coprocessor based on a LMT line (LMTLINE). The LMTLINE is wider than the data-processing width. The processor accelerator sends, to the processor, a response to the instruction. The response is based on completion of the LMT store of the data set in its entirety. The processor accelerator enables the processor to perform useful work in parallel with the LMT store, thereby improving processing performance of the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.