Albert Ma
12Patents
2h-index
11Co-inventors
47Inventor score
Filing activity: Nov 14, 2014 → Feb 21, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9405702B2 | Caching TLB translations using a unified page table walker cache | Physics | 7 | Active |
| US11416405B1 | System and method for mapping memory addresses to locations in set-associative caches | Physics | 2 | Active |
| US11960727B1 | System and method for large memory transaction (LMT) stores | Physics | 1 | Active |
| US10303514B2 | Sharing resources in a multi-context computing system | Emerging Cross-Sectional Technologies | 1 | Active |
| US11474953B2 | Configuration cache for the ARM SMMUv3 | Physics | 0 | Active |
| US9678717B2 | Distributing resource requests in a computing system | Physics | 0 | Active |
| US12282658B1 | System and method for large memory transaction (LMT) stores | Physics | 0 | Active |
| US11620225B1 | System and method for mapping memory addresses to locations in set-associative caches | Physics | 0 | Active |
| US12032488B1 | Circuit and method for translation lookaside buffer (TLB) implementation | Physics | 0 | Active |
| US10078601B2 | Approach for interfacing a pipeline with two or more interfaces in a processor | Physics | 0 | Active |
| US9910776B2 | Instruction ordering for in-progress operations | Physics | 0 | Active |
| US10339054B2 | Instruction ordering for in-progress operations | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.