Partitioning in post-layout circuit simulation
US11960811B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 15, 2022 |
| Grant date | Apr 16, 2024 |
| Priority date | — |
| Expiry date | Apr 15, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
New techniques for the partitioning of big element blocks in a circuit are disclosed. The techniques partition both pre-layout and post-layout circuits. If a post-layout circuit has different simulation results from a pre-layout circuit, the techniques determine where and how “cross-talk” of the RC networks due to RC extraction is changing the circuit physics behavior from the original design of the circuit. A flow of the local circuit simulation of the pre-layout netlist and the post-layout netlist of the same design is presented. A flow of reference or relative or differential circuit simulation of a known design and a new design of the same kind is described. This Abstract is not intended to limit the scope of the claims.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.