Bitline sense amplifier and a memory device with an equalizer
US11961551B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 27, 2022 |
| Grant date | Apr 16, 2024 |
| Priority date | — |
| Expiry date | Jul 9, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4094
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bitline sense amplifier including: an amplifier which is connected between a first sensing bitline and a second sensing bitline, and detects and amplifies a voltage difference between a first bitline and a second bitline in response to a first control signal and a second control signal; and an equalizer which is connected between a first supply line through which the first control signal is supplied and a second supply line through which the second control signal is supplied, and pre-charges the first bitline and the second bitline with a precharge voltage in response to an equalizing control signal, wherein the equalizer includes an equalizing enable transistor in which a source terminal is connected to the first supply line and performs equalizing in response to the equalizing control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.