Multi-program of memory cells without intervening erase operations
US11961565B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 10, 2022 |
| Grant date | Apr 16, 2024 |
| Priority date | — |
| Expiry date | Jul 22, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes an array of memory cells configured as single-level cell memory and control logic operatively coupled with the array of memory cells. The control logic is to perform operations including: causing first data to be programmed to a plurality of memory cells of the array of memory cells, the first data including a first erase distribution programmed below an erase threshold voltage (Vt) level and a first voltage distribution programmed relative to a first Vt level; and causing, without erasing the plurality of memory cells, second data to be programmed to the plurality of memory cells, the second data including a second erase distribution programmed relative to the first Vt level and a second voltage distribution programmed relative to a second Vt level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.