Substrate manufacturing method for realizing three-dimensional packaging
US11961743B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 8, 2021 |
| Grant date | Apr 16, 2024 |
| Priority date | — |
| Expiry date | Dec 12, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L25/16
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a substrate manufacturing method for realizing three-dimensional packaging, which includes: preparing a base plate, the base plate including a dielectric material layer, a first sidewall pad, a first through-hole pillar and a cavity, the cavity being filled with a first metal block; processing a first circuit layer and a second circuit layer, the first circuit layer including a first padding plate and a second metal block, and the second circuit layer including a second padding plate and a plurality of pin pads; processing and laminating interlayer through-hole pillars; processing a third circuit layer and a fourth circuit layer, the third circuit layer including a second sidewall pad and the fourth circuit layer including a routing circuit; and etching to expose the first sidewall pad, the second sidewall pad and the pin pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.