Calibration scheme for a non-linear ADC
US11962318B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 5, 2022 |
| Grant date | Apr 16, 2024 |
| Priority date | — |
| Expiry date | Jan 5, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/445
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In described examples, an analog to digital converter (ADC), having an input operable to receive an analog signal and an output operable to output a digital representation of the analog signal, includes a voltage to delay (VD) block. The VD block is coupled to the input of the ADC and generates a delay signal responsive to a calibration signal. A backend ADC is coupled to the VD block, and receives the delay signal. The backend ADC having multiple stages including a first stage. A calibration engine is coupled to the multiple stages and the VD block. The calibration engine measures an error count of the first stage and stores a delay value of the first stage for which the error count is minimum.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.