Phase mixer non-linearity compensation within clock and data recovery circuitry
US11962676B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2022 |
| Grant date | Apr 16, 2024 |
| Priority date | — |
| Expiry date | Jun 28, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system and method which compensates for phase mixer circuit non-linearities within a clock and data recovery (CDR) system during active operation. The CDR system includes compensation circuitry and phase accumulation circuitry. The compensation circuitry generates a first compensation signal based on a first compensation value. The phase accumulation circuitry receives the first compensation signal and a phase accumulator input update signal. The phase accumulation circuitry combines the first compensation signal with the phase accumulator input update signal to compensate for a first non-linearity within phase mixer (PMI) circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.