Three-dimensional memory device without gate line slits and method for forming the same
US11963356B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2021 |
| Grant date | Apr 16, 2024 |
| Priority date | — |
| Expiry date | Jun 25, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
Abstract
Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a 3D memory device includes a stack structure including a memory block including a plurality of memory cells. The 3D memory device also includes a first top select structure and a bottom select structure in the memory block and aligned with each other vertically; and a second top select structure in the memory block is separated from the first top select structure by at least one of the plurality of memory cells. The first top select structure, the bottom select structure, and the second top select structure each includes an insulating material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.