Integrated circuit device including vertical memory device
US11963361B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 4, 2021 |
| Grant date | Apr 16, 2024 |
| Priority date | — |
| Expiry date | Dec 11, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/27
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device includes: a substrate having a cell region, a peripheral circuit region, and an interconnection region between the cell region and the peripheral circuit region; a first cell stack structure and a second cell stack structure on the first cell stack structure, each including a plurality of insulating layers and a plurality of word line structures alternately stacked on the substrate; and a dummy stack structure located at a same vertical level as the second cell stack structure, and including a plurality of dummy insulating layers and a plurality of dummy support layers alternately stacked in the peripheral circuit region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.