Ternary in-memory accelerator
US11966714B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2022 |
| Grant date | Apr 23, 2024 |
| Priority date | — |
| Expiry date | May 8, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/043
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit of cells used as a memory array and capable of in-memory arithmetic which includes a plurality of signed ternary processing, each signed ternary processing cell includes a first memory cell, adapted to hold a first digital value, a second memory cell, adapted to hold a second digital value, wherein a binary combination of the first digital value and the second digital value establishes a first signed ternary operand, a signed ternary input forming a second signed ternary operand, and a signed ternary output, wherein the signed ternary output represents a signed multiplication of the first signed ternary operand and the second signed ternary operand, a sense circuit adapted to output a subtraction result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.