Robust, efficient multiprocessor-coprocessor interface
US11966737B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 2, 2021 |
| Grant date | Apr 23, 2024 |
| Priority date | — |
| Expiry date | Oct 27, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2200/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for an efficient and robust multiprocessor-coprocessor interface that may be used between a streaming multiprocessor and an acceleration coprocessor in a GPU are provided. According to an example implementation, in order to perform an acceleration of a particular operation using the coprocessor, the multiprocessor: issues a series of write instructions to write input data for the operation into coprocessor-accessible storage locations, issues an operation instruction to cause the coprocessor to execute the particular operation; and then issues a series of read instructions to read result data of the operation from coprocessor-accessible storage locations to multiprocessor-accessible storage locations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.