Use of multiple different variants of floating point number formats in floating point operations on a per-operand basis
US11966740B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 10, 2021 |
| Grant date | Apr 23, 2024 |
| Priority date | — |
| Expiry date | Oct 2, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3812
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor comprising: a register file comprising a group of operand registers for holding data values, each operand register being a fixed number of bits in length for holding a respective data value of that length; and processing logic comprising floating point logic for performing floating point operations on data values in the register file, the floating point logic is configured to process the fixed number of bits in the respective data value according to a floating point format comprising a set of mantissa bits and a set of exponent bits. The processing logic is operable to select between a plurality of different variants of the floating point format, at least some of the variants having a different size sets of mantissa bits and exponent bits relative to one another.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.