Memory with programmable refresh order and stagger time
US11967353B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Sep 21, 2022 |
| Grant date | Apr 23, 2024 |
| Priority date | — |
| Expiry date | Sep 21, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/408
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory devices and systems with programmable refresh order and stagger times are disclosed herein. In one embodiment, a memory device includes a first memory bank group and a second memory bank group. The memory device is configured, in response to a refresh command, to perform a first refresh operation on the first memory bank group at a first time and a second refresh operation on the second memory bank group at a second time after the first time. The memory device is further configured to perform, in response to a read or write command, a read or write operation on the first memory bank group, the second memory bank group, or both the first and second memory bank groups after beginning the first refresh operation and before completing the second refresh operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.