Brian T. Pecha
6Patents
1h-index
7Co-inventors
33Inventor score
Filing activity: Oct 2, 2020 → Sep 21, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US11409674B2 | Memory with improved command/address bus utilization | Physics | 4 | Active |
| US11468938B2 | Memory with programmable refresh order and stagger time | Physics | 1 | Active |
| US11934326B2 | Memory with improved command/address bus utilization | Physics | 0 | Active |
| US11967353B2 | Memory with programmable refresh order and stagger time | Physics | 0 | Active |
| US11335426B2 | Targeted test fail injection | Physics | 0 | Active |
| US11468939B2 | Conditional row activation and access during refresh for memory devices and associated methods and systems | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.