Concurrent compensation in a memory system
US11967356B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 17, 2021 |
| Grant date | Apr 23, 2024 |
| Priority date | — |
| Expiry date | Jun 30, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/36
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An example apparatus may perform concurrent threshold voltage compensation in a memory array with distributed row redundancy. The example apparatus may include a memory cell array having a mat having a plurality of row sections that each include respective prime memory cell rows and a respective redundant memory cell row. The example apparatus may further include a row decoder configured to receive an access command and a prime row address. The row decoder may be configured to, in response to a determination that the prime row address matches a defective prime row address, concurrently initiate a threshold voltage compensation operation on both of a prime row of the respective plurality of prime rows of memory cells of a first row section of the plurality of row sections corresponding to the prime row address and the respective redundant row of a second row section of the plurality of row sections.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.