Dynamically gated search lines for low-power multi-stage content addressable memory
US11967377B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 9, 2021 |
| Grant date | Apr 23, 2024 |
| Priority date | — |
| Expiry date | May 25, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A content addressable memory (CAM) device includes multiple CAM sub-banks Each CAM sub-bank includes an array of CAM cells arranged in rows and columns and partitioned into a first stage and a second stage along a column dimension. Each CAM sub-bank further includes first-stage match lines (MLs), first-stage search line (SL) pairs, second-stage MLs, and second-stage SL pairs. Each second-stage SL pair is coupled to a column of CAM cells in the second stage and is gated by an SL enable (SL_EN signal). Each CAM sub-bank further includes a circuit operative to receive all of the first-stage MLs as input and de-assert the SL_EN signal when none of the first-stage MLs indicate a match. De-assertion of the SL_EN signal blocks a second portion search key from being provided to the second-stage SL pairs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.