Inventor · San Jose, CA, US

Ritesh Garg

5Patents
1h-index
5Co-inventors
33Inventor score

Filing activity: Oct 20, 2020 → Apr 8, 2022

Most-cited inventions

PatentTitleAreaCited byStatus
US11404121B2 Methods for writing ternary content addressable memory devices Physics 1 Active
US11967377B2 Dynamically gated search lines for low-power multi-stage content addressable memory Physics 0 Active
US11557328B2 Simultaneous write and search operation in a content addressable memory Physics 0 Active
US11894054B2 Methods for writing ternary content addressable memory devices Physics 0 Active
US11342022B2 Low-power multi-stage/multi-segment content addressable memory device Physics 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.