Semiconductor memory device
US11967381B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 6, 2021 |
| Grant date | Apr 23, 2024 |
| Priority date | — |
| Expiry date | May 20, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a memory cell array, a row decoder, a plurality of page buffers, and a voltage switching circuit. The memory cell array includes a plurality of memory cells. The row decoder is connected to the memory cell array through word lines. The plurality of page buffers are connected to the memory cell array through bit lines. The voltage switching circuit decodes an operation voltage and transmits the decoded operation voltage to the row decoder. The plurality of page buffers are formed in a first under cell region among first and second under cell regions, the first and second under cell regions being adjacent to each other in a first direction under the memory cell array. At least a portion of the voltage switching circuit is formed in an under slim region that is adjacent to the first under cell region and the second under cell region in a second direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.