Method and apparatus for power saving in semiconductor devices
US11967393B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 10, 2021 |
| Grant date | Apr 23, 2024 |
| Priority date | — |
| Expiry date | May 11, 2042 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a clock gating circuit and a control circuit. The clock gating circuit outputs a gated clock signal based on a clock signal. Transitions of the clock signal are output in the gated clock signal in response to a clock enable signal having an enable value and are disabled from being output in the gated clock signal in response to the clock enable signal having a disable value. The control circuit includes a first portion that operates based on the clock signal. The first portion sets the clock enable signal to the disable value in response to a disable control and sets the clock enable signal to the enable value in response to a wakeup control. The control circuit includes a second portion that operates based on the gated clock signal. The second portion provides the disable control to the first portion during an operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.