Array substrate and display panel
US11967599B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 2, 2022 |
| Grant date | Apr 23, 2024 |
| Priority date | — |
| Expiry date | Jan 19, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/443
Abstract
An array substrate and a display panel. The array substrate provided in the embodiments of the present application includes: a base including a flat portion and a recess portion so that the base includes a concave hole corresponding to the bending area; a semiconductor component layer provided on the base and including a plurality of interlayer insulation layers and a plurality of metal layers, the interlayer insulation layers being not aligned horizontally in the peripheral area and the wire switching area to form a stepped hole including a first hole and a second hole, wherein a third metal layer of the metal layers extends along a sidewall and a bottom of the stepped hole and is electrically connected to a first metal layer of the metal layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.