Dynamic status registers array
US11972144B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2021 |
| Grant date | Apr 30, 2024 |
| Priority date | — |
| Expiry date | Apr 15, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and devices for dynamic status registers array are described. An apparatus may include one or more memory dice coupled with a data bus. The apparatus may further include a controller coupled with each of the memory dice via the data bus that is configured to transmit a first command associated with a first operation to a first memory die. The first command may assign an associated operation (e.g., the first operation) to a queue slot of a status bank that is associated with at least the first memory die. The controller may further transmit second command to the first memory die to request a status of the first operation. The controller may receive a status of the first operation via a channel (e.g., a first channel) of the data bus that is based on the assigned queue slot of the status bank.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.