Cooperative instruction prefetch on multicore system
US11972263B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Oct 25, 2022 |
| Grant date | Apr 30, 2024 |
| Priority date | — |
| Expiry date | Oct 25, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3888
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aspects of the disclosure are directed to methods, systems, and apparatuses using an instruction prefetch pipeline architecture that provides good performance without the complexity of a full cache coherent solution deployed in conventional CPUs. The architecture can include components which can be used to construct an instruction prefetch pipeline, including instruction memory (TiMem), instruction buffer (iBuf), a prefetch unit, and an instruction router.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.