Receiver for receiving multi-level signal and memory device including the same
US11972831B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 27, 2022 |
| Grant date | Apr 30, 2024 |
| Priority date | — |
| Expiry date | Nov 4, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K7/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A receiver that receives a multi-level signal includes a pre-amplifier circuit, a slicer circuit and a decoder circuit. The pre-amplifier circuit generates a plurality of intermediate data signals based on an input data signal and a plurality of reference voltages. The slicer circuit generates a plurality of decision signals based on the plurality of intermediate data signals and a clock signal. The decoder circuit generates output data based on the plurality of decision signals. The pre-amplifier circuit includes a first circuit and a second circuit. The first circuit generates one of the plurality of intermediate data signals based on the input data signal and one of the plurality of reference voltages, and has a first structure. The second circuit generates another one of the plurality of intermediate data signals based on the input data signal and another one of the plurality of reference voltages, and has a second structure different from the first structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.