Method of manufacturing a semiconductor package including correcting alignment error while forming redistribution wiring struture
US11972966B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2020 |
| Grant date | Apr 30, 2024 |
| Priority date | — |
| Expiry date | Nov 1, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a method of manufacturing a semiconductor package, a plurality of semiconductor chips are encapsulated in a carrier to provide encapsulated semiconductor chips. A first surface of the encapsulated semiconductor chips includes chip pads exposed from a first surface of the carrier. An alignment error of each of the semiconductor chips with respect to the carrier is measured. A redistribution wiring structure may be formed on the first surface of the carrier. Correction values for each layer of the redistribution wiring structure may be reflected while forming the redistribution wiring structure in order to correct the alignment error while forming the redistribution wiring structure. The redistribution wiring structure may have redistribution wirings electrically connected to the chip pads on the first surface of the carrier. Outer connection members may be formed on the redistribution wiring structure and may be configured to be electrically connected to the outermost redistribution wirings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.