Self-aligned barrier for metal vias
US11972974B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 13, 2022 |
| Grant date | Apr 30, 2024 |
| Priority date | — |
| Expiry date | Apr 10, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An IC structure includes a transistor, a source/drain contact, a metal oxide layer, a non-metal oxide layer, a barrier structure, and a via. The transistor includes a gate structure and source/drain regions on opposite sides of the gate structure. The source/drain contact is over one of the source/drain regions. The metal oxide layer is over the source/drain contact. The non-metal oxide layer is over the metal oxide layer. The barrier structure is over the source/drain contact. The barrier structure forms a first interface with the metal oxide layer and a second interface with the non-metal oxide layer, and the second interface is laterally offset from the first interface. The via extends through the non-metal oxide layer to the barrier structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.